Semiconductor device including fuse elements and bonding pad

ABSTRACT

A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device.

More specifically, the present invention relates to a semiconductordevice having a portion used as a fuse.

2. Background Art

In recent years, accompanying the miniaturization, and increase in thecapacity and speed of semiconductor devices, a rescuing method forsecuring the yield is taken in a semiconductor manufacturing processwherein spare memory cells are previously prepared in a semiconductordevice, and when a defective bit is found, the defective bit is replacedby a spare memory cell. As the method for replacing the defective bit toa spare memory cell, a method wherein the portion to be used as a fuseis previously provided in a wiring layer, and a program to blow thefuse, whereby to transmit a signal to use the spare memory cell, isprovided.

As a method to blow the fuse, the laser trimming system wherein laserbeams are radiated onto the fuse is widely used. In this case, ingeneral, YAG laser or YLF laser is often used to radiate laser beams.

As the material for the fuse wiring, Al, which has relatively lowmelting point and boiling point, is suited. The wiring used as a fuse isoften formed utilizing the wiring layer used in the formation of otherwirings. On the other hand, in order to form fine wirings and to reducethe wiring resistance, Cu wirings have often been used. However, sinceCu has higher melting point and boiling point than Al, blowing usingconventional YAG or YLF laser is difficult, and when a conventionalblowing method is used, it is difficult that a Cu wiring is used as afuse.

It is also difficult to perform Au or Al wire bonding on a Cu wiring,and Al is generally used for the uppermost wiring layer that forms theportion used as the bonding pad. A passivation film for protecting thesurface of a semiconductor chip is also formed on the uppermost Alwiring, and a silicon nitride film is often used as the passivationfilm.

It has generally known that when an Al wiring is blown using laserbeams, the Al wiring is easily cut when a silicon oxide film is formedon the Al wiring. On the other hand, since a silicon nitride filmabsorbs much laser beams, and has a high melting point, the blow of theAl wiring in the silicon nitride film may produce blow residues, andcannot be performed properly.

Therefore, when a silicon nitride film is used as the passivation film,it is difficult to use the Al wiring in the uppermost layer as the fusewiring. For this reason, an Al wiring is normally formed in the siliconoxide film formed below the uppermost wiring layer to used as the fusewiring. Generally, in order to constitute a fuse wiring, at least twolayers of Al wiring layers, that is, an Al wiring layer for the bondingpad, and an Al wiring layer for the fuse formed in the silicon oxidefilm, are required. However, the structure wherein an insulating film isformed between the two Al wiring layers is apt to be cracked by thevibration when the wires are fixed to the bonding pad.

Although a silicon nitride film or a silicon oxide film is normallyformed using a P-CVD method, the adjacent fuses may be damaged when afuse is blown because a thin film formed using a P-CVD method is thelacking in flatness.

On the other hand, in order to use an Al wiring on the uppermost layer,and to blow the Al wiring properly, it is considered to make the Alwiring thin. The Al wiring is normally formed so as to have a thicknessof 600 to 800 nm; however, if the thickness of the Al wiring is as thinas 100 to 400 nm, it is easily blown even if the Al wiring is present inthe silicon nitride film. However, the reduction of the thickness of theAl wiring may lead to the deterioration of the bonding characteristicsof the bonding pad, and cracks may occur in the interlayer insulatingfilm under the Al wiring during bonding or testing, the bonding strengthmay lower, and the pad may be delaminated. Therefore, simply thinningthe Al wiring is not preferable (e.g., refer to Patent References ofJapanese Patent Laid-Open No. 2002-203902 and of Japanese PatentLaid-Open No. 2002-110799).

SUMMARY OF THE INVENTION

Therefore, the present invention proposes an improved semiconductordevice and a method for manufacturing such a semiconductor device so asto inhibit damage to the adjacent fuse, and to ensure that the only thetarget fuse is blown.

According to one aspect of the present invention, a semiconductor devicecomprises a lower-layer substrate including at least one metal layer, afuse formed above the lower-layer substrate, a silicon oxide film formedon the fuse and on the exposed portion of the surface of the lower-layersubstrate, and a silicon nitride film formed on the silicon oxide film.The fuse is the top of metal layers in the semiconductor device and isformed from metal including Al. The portion of the silicon oxide filmformed on the surface of the lower-layer substrate is thicker than thefuse. The silicon nitride film has an opening above the portion wherethe fuse is formed.

According to another aspect of the present invention, a semiconductordevice comprises a lower-layer substrate including at least one metallayer, a fuse formed above the lower-layer substrate, and an insulatingfilm formed on the fuse and on the exposed portion of the surface of thelower-layer substrate. The fuse is the top of metal layers in thesemiconductor device and is formed from metal including Al. Theinsulating film includes a first insulating film and a second insulatingfilm, and the portion of the insulating film formed on the surface ofthe lower-layer substrate is thicker than the fuse.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view for illustrating the structure of asemiconductor device 100 in the first embodiment of the presentinvention;

FIG. 2 is a schematic sectional view in the A-A′ direction of thesemiconductor device 100 in FIG. 1;

FIG. 3 is a schematic perspective top view of the wiring layers of thesemiconductor device 100;

FIG. 4 is a schematic top view of the semiconductor device 100;

FIG. 5 is a flow diagram for illustrating the manufacturing process ofthe semiconductor device 100 in the first embodiment of the presentinvention;

FIG. 6 is a schematic sectional view for illustrating a semiconductordevice 200 in the second embodiment of the present invention;

FIG. 7 is a schematic diagram showing the cross section of thesemiconductor device 200 in FIG. 6 in the A-A′ direction;

FIG. 8 is a schematic sectional view for illustrating a semiconductordevice in the second embodiment of the present invention;

FIG. 9 is a schematic sectional view for illustrating a semiconductordevice 300 in the third embodiment of the present invention;

FIG. 10 is a schematic diagram showing the cross section of thesemiconductor device 300 in FIG. 9 in the A-A′ direction;

FIG. 11 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 300;

FIG. 12 is a schematic sectional view for illustrating a semiconductordevice 400 in the fourth embodiment of the present invention;

FIG. 13 is a schematic diagram showing the cross section of thesemiconductor device 400 in FIG. 12 in the A-A′ direction;

FIG. 14 is a schematic sectional view for illustrating a semiconductordevice 500 in the fifth embodiment of the present invention;

FIG. 15 is a schematic diagram showing the cross section of thesemiconductor device 500 in FIG. 14 in the A-A′ direction;

FIG. 16 is a schematic sectional view for illustrating a semiconductordevice 600 in the sixth embodiment of the present invention;

FIG. 17 is a schematic diagram showing the cross section of thesemiconductor device 600 in FIG. 16 in the A-A′ direction;

FIG. 18 is a schematic sectional view for illustrating a semiconductordevice 700 in the seventh embodiment of the present invention;

FIG. 19 is a schematic diagram showing the cross section of thesemiconductor device 700 in FIG. 18 in the A-A′ direction;

FIG. 20 is a schematic sectional view for illustrating a semiconductordevice 800 in the eighth embodiment of the present invention;

FIG. 21 is a schematic diagram showing the cross section of thesemiconductor device 800 in FIG. 20 in the A-A′ direction;

FIG. 22 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 800 in the eighth embodiment of the presentinvention;

FIG. 23 is a schematic sectional view for illustrating a semiconductordevice 900 in the ninth embodiment of the present invention;

FIG. 24 is a schematic diagram showing the cross section of thesemiconductor device 900 in FIG. 23 in the A-A′ direction;

FIG. 25 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 900 in the ninth embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiments of the present invention will be described belowreferring to the drawings. In the drawings, the same or like parts willbe denoted by the same reference numerals, and the description thereofwill be simplified or omitted.

First Embodiment

FIG. 1 is a schematic sectional view for illustrating the structure of asemiconductor device 100 in the first embodiment of the presentinvention. FIG. 2 is a schematic sectional view in the A-A′ direction ofthe semiconductor device 100 in FIG. 1. FIG. 3 is a schematicperspective top view of the wiring layers of the semiconductor device100, and FIG. 4 is a schematic top view of the semiconductor device 100.

As FIGS. 1 and 2 show, in the semiconductor device 100, an interlayerinsulating film 4 is formed on an Si substrate 2, and Cu wirings 6 areformed in the interlayer insulating film 4. An interlayer insulatingfilm 8 is formed on the surfaces of the Cu wirings 6, and on theexposing surface of the interlayer insulating film 4. Via holes 10 thatpass through the interlayer insulating film 8 are formed in thelocations of the interlayer insulating film 8 corresponding to thelocations of the Cu wirings 6, and are filled with tungsten.

The fuse portion 110 and the bonding-pad portion 120 of thesemiconductor device 100 have a fuse wiring 12 and a bonding pad 14formed on the interlayer insulating film 8, respectively. The fusewiring 12 and the bonding pad 14 are Al films formed in the same step,and have the same thickness d_(f). Specifically, the thickness d_(f) isfrom approximately 400 nm to 900 nm, in the first embodiment. The widthW_(a) in FIG. 2 is from approximately 0.8μ m to 1.2μ. As FIG. 3 shows,when the fuse wiring 12 is viewed from the above, laterally long andliner Al wiring layers, which are laterally long and narrow in thesectional direction of FIG. 1, are arranged in the depth direction(i.e., in FIG. 1, the direction vertical to the page). When the bondingpad 14 is viewed from the above, it is formed in a rectangular shape.

A silicon oxide film 16 is formed on the fuse wiring 12, the bonding pad14, and the portion of the interlayer insulating film 8 exposed on thesurface. The silicon oxide film 16 is formed along the step between thefuse wiring 12 and the bonding pad 14 on the surface of the interlayerinsulating film 8 and has a substantially uniform thickness. Therefore,the thickness d_(a) of the silicon oxide film 16 in the portion of thesilicon oxide film 16 whereon the fuse wiring 12 is not formed, that isthe portion of the silicon oxide film 16 directly contacting theinterlayer insulating film 8, is equal to the thickness d_(b) of thesilicon oxide film 16 formed on the fuse wiring 12. The silicon oxidefilm 16 is formed so that the thickness thereof d_(a) and d_(b) becomesthicker than the thickness d_(f) of the fuse wiring 12. In considerationof ease of laser trimming, a thickness difference between the thicknessd_(f) of the wiring 12 and thickness d_(a), d_(b) of the silicon oxidefilm 16 is less than approximately 400 nm.

As FIGS. 1 and 4 show, the silicon oxide film 16 has an opening in thebonding pad portion 120 formed so as to expose a part of the surface ofthe bonding pad 14.

A silicon nitride film 18 is formed on the silicon oxide film 16. Thesilicon nitride film 18 has a substantially uniform thicknessthroughout. In the fuse portion 110, as FIG. 4 shows, the siliconnitride film 18 has an opening in the portion whereon the fuse wiring 12is formed. Namely, the silicon nitride film 18 is not laminated on thesilicon oxide film 16 above the fuse wiring 12, but the silicon nitridefilm 18 is laminated only on the portion whereon the fuse wiring 12 isnot formed. On the other hand, in the bonding pad portion 120, thesilicon nitride film 18 has an opening formed so as to expose a part ofthe surface of the bonding pad 14 in the same manner as the siliconoxide film 16. From the openings formed in the silicon oxide film 16 andsilicon nitride film 18, the bonding pad 14 can be connected to thewire.

FIG. 5 is a flow diagram for illustrating the manufacturing process ofthe semiconductor device 100 in the first embodiment of the presentinvention. The method for manufacturing a semiconductor device 100 inthe first embodiment of the present invention will be described belowreferring to FIGS. 1 to 5.

First, in the normal process, an interlayer insulating film 4 is formedon an Si substrate 2 (Step S102), and Cu wirings 6 are formed in theinterlayer insulating film 4 using a Damascene method (Step S104).Thereafter, an interlayer insulating film 8 is formed on the Cu wiring 6and the interlayer insulating film 4 (Step S106), and via holes 10 areformed by etching so as to pass through the interlayer insulating film 8to the surfaces of the Cu wirings 6 (Step S108). The via holes 10 arefilled with tungsten (Step S110), and planarization by CMP (chemicalmechanical polishing) is performed until the surface of the interlayerinsulating film 8 is exposed (Step S112).

Next, an Al film is formed on the tungsten in the via holes 10 and theinterlayer insulating film 8 (Step S114). The Al film is formed so as tobe from approximately 400 nm to 900 nm thick. Then, the Al film isetched (Step S116), and fuse wirings 12 are formed in the fuse portion110 and bonding pads 14 are formed in the bonding pad portion 120.

Next, a silicon oxide film 16 is formed (Step S118). Here, a P-CVD(plasma chemical vapor deposition) method is used. Thereby, the step ofthe lower-layer base material, that is, the step formed by fuse wirings12 and the bonding pad 14 formed on the interlayer insulating film 8, isalmost correctly reflected to form a conformal silicon oxide film havinga uniform thickness d_(a) and d_(b).

Next, a silicon nitride film 18 is formed on the silicon oxide film 16(Step S120). Here, the silicon nitride film 18 is formed using a P-CVDmethod, and becomes a film on a uniform thickness almost correctlyreflecting the step of the surface of the silicon oxide film 16. Thesilicon oxide film 16 is formed so that the thickness difference betweenthe thickness d_(a), d_(b) of the silicon oxide film 16 and thethickness d_(f) of the fuse wiring 12 is thinner than approximately 400nm or so.

Next, openings are formed in the silicon nitride film 18 and the siliconoxide film 16 (Steps S122 and S124). Specifically, and in the bondingpad portion 120, openings are formed in the silicon nitride film 18 andthe silicon oxide film 16 above the bonding pad 14 so that a part of thebonding pad 14 is exposed (Step S122). Thereafter, an opening is formedin the fuse portion 110 by etching so that the surface of the siliconoxide film 16 is exposed above the fuse wirings 12 (Step S124).

As described above, the semiconductor device 100 is formed.

According to the first embodiment, as described above, the fuse wiring12 can be formed using the wiring layer formed in the uppermost layer ofthe Al wiring layers formed to form the bonding pad 14, that is, thewiring layer formed in the semiconductor device 100. Also, this Aiwiring is embedded in the silicon oxide film 16. Here, although thesilicon nitride film 18 is laminated on the silicon oxide film 16, sincethe silicon nitride film 18 has an opening on the portion where of thefuse wiring 12 is formed, and the silicon nitride film 18 is not formedon the fuse wiring 12.

According to the first embodiment, the fuse wiring 12 is an Al wiringformed in the uppermost layer of wiring layers, and since the fusewiring 12 is buried in the silicon oxide film 16, the silicon nitridefilm 18 is not formed on the fuse wiring 12. Therefore, the fuse wiring12 can be easily blown inhibiting the formation of blow residues.

Since the uppermost Al wiring can be utilized as a fuse, there is noneed to form another layer of the Al layer underneath the uppermost Alwiring. Therefore, the formation of the structure having an insulatingfilm sandwiched between Al wirings can be avoided, and cracking duringwire bonding can be inhibited. There is no need to form two layers of Alwirings in order to form the fuse, and the Al layer used for forming thebonding pad 14 can also be used for forming the fuse wiring 12.Therefore, the size of the entire semiconductor device 100 can bereduced, and the throughput in the manufacture of semiconductor devicescan be improved.

Although the silicon nitride film 18 has openings on the fuse wiring 12and on the bonding pad 14, other portions of the semiconductor device100 are covered with the silicon nitride film 18. Therefore, theinfiltration of moisture into the chip can be prevented, and thereliability of the semiconductor device 100 can be secured.

In the first embodiment, the thickness d_(a) of the silicon oxide film16 is thicker than the thickness d_(f) of the fuse wiring 12. Thereby,when the fuse wiring 12 is blown, damage to other adjacent fuse wiringscan be prevented.

In the first embodiment, there was described the case where the fusewiring 12, the silicon oxide film 16 and the like are formed on thelower-layer substrate wherein the interlayer insulating film 4, the Cuwiring 6, and the interlayer insulating film 8 are formed on the Sisubstrate 2. However, the present invention is not limited thereto, butother structures may also be used. Also, the layer whereon the fusewiring 12 is formed is not limited to the layer whereon the bonding pad14 is formed.

Also in the first embodiment, there was described the case where thefuse wiring 12 is constructed of Al. However, the fuse wiring in thepresent invention is not limited thereto, but other material may alsoconstitute the fuse wiring. For example, the fuse wiring is constructedof metal including Ti, Ta, Cu or the like. Further, the fuse wiring maybe constructed of lamination layer of metal films.

Also in the first embodiment, there was described the case where thethickness d_(f) of the fuse wiring 12 is from approximately 400 to 900nm and where the thickness d_(a), d_(b) of the silicon oxide film isthicker by approximately 400 nm or less than the thickness d_(f).However, the thickness d_(f), d_(a) and d_(b) in the present inventionis limited thereto. In consideration of ease in fuse trimming or thelike, the thickness of them may be decided, suitably. Provided that if alayer including Al existed under the fuse wiring 12, the thickness ofthe fuse wiring 12 is preferably thicker than that of the layerincluding Al.

Also in the first embodiment 1, there was described the case where thesilicon oxide film 16 and the silicon nitride film 18 are formed using aP-CVD method. However, the present invention is not limited to the useof a P-CVD method, but these may be formed using other methods.

Second Embodiment

FIG. 6 is a schematic sectional view for illustrating a semiconductordevice 200 in the second embodiment of the present invention. FIG. 7 isa schematic diagram showing the cross section of the semiconductordevice 200 in FIG. 6 in the A-A′ direction.

As FIGS. 6 and 7 show, the semiconductor device 200 resembles thesemiconductor device 100. Also in the semiconductor device 200, aninterlayer insulating film 4 is formed on an Si substrate 2, Cu wirings6 are buried on the interlayer insulating film 4, furthermore, aninterlayer insulating film 8 is formed on the interlayer insulating film4 and the Cu wirings 6, and via holes 10 filled with tungsten are formedin the interlayer insulating film 8. Also in the fuse portion 210, afuse wiring 12 is formed, and in the bonding pad portion 220, a bondingpad 14 is formed. The fuse wiring 12 and the bonding pad 14 has the samethickness d_(f) as in the first embodiment.

As in the semiconductor device 100, a silicon oxide film 20 is formed onthe fuse wiring 12 and the bonding pad 14, and the portion of theinterlayer insulating film 8 exposed on the surface. However, unlike thesemiconductor device 100, the silicon oxide film 20 has a ridged portion22 formed on the fuse wiring 12, and a flat portion 24 having a flatsurface formed on the interlayer insulating film 8. The thickness of theflat portion 24 is d_(a). The thickness from near the peak of the ridgedportion 22 to the surface of the fuse wiring 12 is d_(b). The thicknessd_(a) is substantially the same as the thickness d_(b), and is somewhatthicker than the thickness d_(f) of the fuse wiring 12. Also as in thefirst embodiment, the silicon oxide film 20 has an opening on thebonding pad 14.

On the silicon oxide film 20, a silicon nitride film 26 is formed in auniform thickness almost correctly reflecting the step of the surface ofthe silicon oxide film 20. Namely, the surface of the silicon nitridefilm 26 is ridged on the ridged portion 22 on the silicon oxide film 20,and is flat on the flat portion 24. Also as in the first embodiment, thesilicon nitride film 26 has openings on the opening portion of thesilicon oxide film 20 on the bonding pad 14, and the portion whereon thefuse wiring 12 is formed.

Next, a method for manufacturing the semiconductor device 200 in thesecond embodiment of the present invention will be described.

First, as described for the first embodiment, by performing steps S102to S116, the state wherein the fuse wiring 12 is formed in the fuseportion 210, and the bonding pad 14 is formed in the bonding pad portion220 is completed.

Next, as in the first embodiment, a silicon oxide film 20 is formed. Inthe second embodiment, however, the P-CVD method used in the firstembodiment is not used, but an HDP-CVD (high density plasma chemicalvapor deposition) method is used. The HDP-CVD method is a method forforming a film by using high-density plasma while impressing a highvoltage to a CVD apparatus. Unlike conventional P-CVD wherein aconformal film is formed correctly reflecting the step of thelower-layer base material, in the HDP-CVD method, etching is performedsimultaneously with film forming at the corners (shoulders) of the step,that is, the portion with a steep angle. As a result, as FIGS. 6 and 7show, a diagonally inclined film is formed on the portion having a stepin the lower layer, and particularly on a fine fuse wiring 12, atriangularly ridged shape is formed.

Next, in the same manner as the first embodiment, a silicon nitride film26 is formed on the silicon oxide film 20 using a P-CVD method (StepS120). The silicon nitride film 26 is correctly reflected to the step ofthe lower layer, and becomes a thin film having a uniform thickness.

Furthermore, as in the first embodiment, openings are formed in thesilicon nitride film 26 and the silicon oxide film 20 (Steps S122,S124). Specifically, the silicon nitride film 26 and the silicon oxidefilm 20 on the bonding pad 14 are etched to form the openings.Thereafter, the silicon nitride film 26 above the fuse wirings 12 isetched to form an opening.

As described above, the semiconductor device 200 is formed.

In the second embodiment as described above, the silicon oxide film 20has a ridged portion 22 and a flat portion 24. The ridged portion 22 isformed on the fuse wiring 12, and continuing to the ridged portion 22,the flat portion 24 is formed on the interlayer insulating film 8 whereon the fuse wiring 12 is not formed. Thereby, the side portion of thefuse wiring 12 can be covered with the silicon oxide film 20, while theentire thickness of the silicon oxide film 20 on the fuse wiring 12 canbe thinned. Therefore, fuse blow can be performed surely, and damage toadjacent fuses can be inhibited.

In the second embodiment, the silicon oxide film 20 has a ridged portion22 on the fuse wiring 12. Accordingly, the laser beams for blowing thefuse wiring can be refracted at the ridged portion 22 and concentratedon the surface of the fuse wiring 12. Therefore, the fuse to be blowncan be blown more securely without damaging adjacent fuses.

In the second embodiment also, as in the first embodiment, the fusewiring 12 is an Al wiring formed on the uppermost layer of wiringlayers, and the fuse wiring 12 is buried in the silicon oxide film 20and the silicon nitride film 26 is not formed on the fuse wiring 12.Therefore, the fuse wiring 12 can be easily blown without blow residues.In the semiconductor device 200 also, since the formation of thestructure wherein an insulating film is sandwiched between Al wiringscan be avoided, the size reduction and the throughput improvement of theentire semiconductor device 200 can be achieved while inhibitingcracking that may occur during wire bonding. Furthermore, in thesemiconductor device 200, since the silicon nitride film 26 is formed asa passivation film on the uppermost layer, the infiltration of moistureinto the chip can be prevented, and the reliability of the semiconductordevice 200 can be secured.

Also in the second embodiment, the thickness d_(a) of the silicon oxidefilm 20 is made thicker than the thickness d_(f) of the fuse wiring 12.Thereby, when the fuse wiring 12 is blown, damage to adjacent other fusewirings 12 can be inhibited.

In the second embodiment, the silicon oxide film 20 consisting of aridged portion 22 and a flat portion 24 is formed using an HDP-CVDmethod. According to this method, the silicon oxide film 20 of such ashape can be easily formed; however, in the present invention, themethod for forming a silicon oxide film is not limited to the HDP-CVDmethod described in the second embodiment.

Also in the second embodiment, the width of the ridged portion 22 iswider than that of the fuse wiring 12 as shown in FIG. 6 and FIG. 7.However, the present invention is not limited there to, but the width ofthe ridged portion 22 may be narrower than that of the fuse wiring asshown in FIG. 8.

Since other parts are same as in the first embodiment, the descriptionthereof will be omitted.

Third Embodiment

FIG. 9 is a schematic sectional view for illustrating a semiconductordevice 300 in the third embodiment of the present invention. FIG. 10 isa schematic diagram showing the cross section of the semiconductordevice 300 in FIG. 9 in the A-A′ direction.

As FIGS. 8 and 9 show, the semiconductor device 300 in the thirdembodiment resembles the semiconductor device 200 described in thesecond embodiment. Similar to the semiconductor device 200, thesemiconductor device 300 also includes an Si substrate 2, an interlayerinsulating film 4, Cu wirings 6, an interlayer insulating film 8, andvia holes 10 filled with tungsten. Also in the fuse portion 310, a fusewiring 12 is formed, and in the bonding pad portion 320, a bonding pad14 is formed. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the first embodiment.

However, unlike the semiconductor device 200, a silicon nitride film 30is directly formed in place of the silicon oxide 20 on the fuse wiring12, the bonding pad 14, and the portion of the interlayer insulatingfilm 8 exposed to the surface. The silicon nitride film 30 has a ridgedportion 32 formed on the fuse wiring 12, and a flat portion 34 having aflat surface formed on the interlayer insulating film 8. The thicknessof the flat portion 34 is d_(a). The thickness of the ridged portion 32between the vicinity of the peak and the surface of the fuse wiring 12is d_(b). The thickness d_(a) is equal to the thickness d_(b), and issomewhat thicker than the thickness d_(f) of the fuse wiring 12. Anopening is formed in the silicon nitride film 30, so that a part of thesurface of the bonding pad 14 is exposed.

FIG. 11 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 300.

The method for manufacturing the semiconductor device 300 in the thirdembodiment of the present invention will be described below referring toFIGS. 8 to 10.

First, in the same manner described in the second embodiment, byperforming steps S102 to S116, the state wherein the fuse wiring 12 isformed in the fuse portion 310, and the bonding pad 14 is formed in thebonding pad portion 320 is completed.

Here, in place of the silicon oxide film 20 in the second embodiment, asilicon nitride film 30 is formed (Step S302). The silicon nitride film30 is also formed using an HDP-CVD method. When the HDP-CVD method isused, etching is performed simultaneously with film forming at thecorners (shoulders) of the step, that is, the portion with a steepangle. As a result, as FIGS. 8 and 9 show, a diagonally inclined film isformed on the portion having a step in the lower layer, and particularlyon a fine fuse wiring 12, a triangularly ridged shape is formed.

Next, an opening is formed in the silicon nitride film 30 so that a partof the surface of the bonding pad 14 is exposed (Step S304). Thereby,the semiconductor device 300 is formed. Unlike the first and the secondembodiments, no openings are formed in the portion of the siliconnitride film 30 present on the fuse wiring 12.

According to the third embodiment, as described above, the siliconnitride film 30 is directly formed on the fuse wiring 12. As describedabove, if a silicon nitride film is formed on the Al wiring as usual,laser beams are absorbed in the silicon nitride film; therefore, fuseblow may be failed. However, when the ridged silicon nitride film 30 isformed on the fuse wiring 12 using an HDP-CVD method, the entirethickness of the silicon nitride film 30 on the fuse wiring 12 can bethinned. Therefore, fuse blow can be performed easily and properly.

Also in the third embodiment, the thickness d_(a) of the silicon nitridefilm 30 is made thicker than the thickness d_(f) of the fuse wiring 12.Also, since the silicon nitride film 30 has higher film stress and filmdensity than the silicon oxide layer, a larger effect for inhibitingdamage to adjacent fuses due to compression from the side of the fusewiring 12. Therefore, as a result, good fuse-blow properties can beobtained.

Also in the semiconductor device 300, since the silicon nitride film 30formed on the uppermost layer functions as a passivation film, theinfiltration of moisture into the chip can be prevented, and thereliability of the semiconductor device 300 can be secured.

According to the third embodiment, only the silicon nitride film 30 isformed on the fuse wiring 12. Therefore, there is no need to form apassivation film consisting of a silicon nitride film separately as inthe case when the silicon oxide film is formed. Therefore, themanufacturing process of the semiconductor device can be simplified, andthe throughput can be improved.

Also in the third embodiment, the fuse wiring 12 is an Al wiring formedon the uppermost layer of the wiring layers, the formation of thestructure wherein an insulating film is sandwiched between Al wiringscan be avoided. Therefore, the size reduction and the throughputimprovement of the entire semiconductor device 300 can be achieved whileinhibiting cracking that may occur during wire bonding.

Since other parts are same as in the second embodiment, the descriptionthereof will be omitted.

Fourth Embodiment

FIG. 12 is a schematic sectional view for illustrating a semiconductordevice 400 in the fourth embodiment of the present invention. FIG. 13 isa schematic diagram showing the cross section of the semiconductordevice 400 in FIG. 12 in the A-A′ direction.

The semiconductor device 400 in the fourth embodiment resembles thesemiconductor device 300 described in the third embodiment. Similar tothe semiconductor device 300, the semiconductor device 400 also includesan Si substrate 2, an interlayer insulating film 4, Cu wirings 6, aninterlayer insulating film 8, and via holes 10 filled with tungsten. Inthe fourth embodiment, F-doped silicon oxide (SiOF) film is especiallyused as entire or a part of the interlayer insulating film 8 or theinterlayer insulating film 4.

As in the semiconductor device 300, a fuse wiring 12 is formed in thefuse portion 410, and a bonding pad 14 is formed in the bonding padportion 420. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the first embodiment.

In the semiconductor device 400, unlike the semiconductor device 300, asilicon oxide film 40 is formed on the fuse wiring 12, the bonding pad14, and the portion of the interlayer insulating film 8 exposed to thesurface. The silicon oxide film 40 in the semiconductor device 400 has auniform thickness, and has a shape along the step formed in the fusewiring 12. Also, the silicon oxide film 40 is a thin film thinner thanthe thickness d_(f) of the fuse wiring 12.

In the semiconductor device 400, a silicon nitride film 42 is formed onthe silicon oxide film 40. The silicon nitride film 42 a ridged portion44 on the fuse wiring 12, and a flat portion 46 on the interlayerinsulating film 8.

Here, the total thickness of the insulating films formed on theinterlayer insulating film 8, that is the total thickness of the siliconoxide film 40 and the flat portion 46 of the silicon nitride film 42, isd_(a). The total thickness of the insulating films formed on the fusewiring 12, that is the total thickness of the silicon oxide film 40 andthe ridged portion 44 of the silicon nitride film 42 at the thickestportion, is d_(a). The film thickness d_(a) is substantially equal tothe film thickness d_(b), and is somewhat thicker than the thicknessd_(f) of the fuse wiring 12.

The silicon oxide film 40 and the silicon nitride film 42 have openingsin the portion whereon the bonding pad 14 is formed, and from thisportion, the connection of wires can be performed.

The method for manufacturing the semiconductor device 400 resembles tothe method for manufacturing the semiconductor device 300. Specifically,by first performing steps S102 to S116, the fuse wiring 12 is formed inthe fuse portion 410, and a bonding pad 14 is formed in the bonding padportion 420.

Next, the silicon oxide film 40 is formed. Here, the silicon oxide film40 is formed using a P-CVD method, and the film formation is completedat the stage wherein the thickness of the silicon oxide film 40 is apredetermined thickness thinner than the thickness of the fuse wiring12. Thereby, correctly reflecting the step of the fuse wiring 12, thebonding pad 14, and the like on the interlayer insulating film 8, thesilicon oxide film 40 having irregularity on the surface is formed.

Next, the silicon nitride film 42 is formed on the silicon oxide film40. Here, the silicon nitride film 42 is formed using an HDP-CVD method.While forming the silicon nitride film 42, etching is performedsimultaneously with film forming at the corners (shoulders) of the step,that is, the portion with a steep angle. As a result, as FIGS. 11 and 12show, a diagonally inclined film is formed on the portion having a stepin the lower layer, and particularly on a fine fuse wiring 12, atriangularly ridged shape is formed.

Next, as in the third embodiment, openings are formed in the siliconoxide film 40 and the silicon nitride film 42 so that a part of thesurface of the bonding pad 14 is exposed.

As described above, the semiconductor device 400 is formed.

In the fourth embodiment, as described above, a thin film consisting ofthe silicon oxide film 40 is formed underneath the silicon nitride film42. The temperature of the silicon nitride film formed using an HDP-CVDmethod may become as high as 400° C. or above. Therefore, voids may beproduced in the fuse wiring 12. Also when the F-doped silicon oxide(SiOF) film is used in all or a part of the underlying interlayerinsulating film 8 or the interlayer insulating film 4 in order to lowerthe dielectric, constant, since the silicon nitride film has a highblocking property for F, it is considered that the F diffused in theinterlayer insulating film 8 may pile up on the boundary to the siliconnitride film. As a result, the blistering of delaminating of theinterlayer insulating film 8 may occur. However, according to the fourthembodiment, the silicon oxide film 40 is formed between the siliconnitride film 42 and the interlayer insulating film 8. Therefore, defectssuch as the voids in the Al wiring and the blistering or delaminating ofthe interlayer insulating film 8 can be inhibited.

Also in the fourth embodiment, the total thickness d_(a) of the siliconoxide film 40 and the silicon nitride film 42 is made thicker than thethickness d_(f) of the fuse wiring 12. Thereby, when the fuse wiring 12is blown, damage to adjacent other fuse wirings 12 can be inhibited.

In addition, the same effects as in the third embodiment can be obtainedalso in the semiconductor device 400 in the fourth embodiment.

In the fourth embodiment, the case wherein SiOF is used in all or a partof the interlayer insulating film 8 is described. This is because thesilicon oxide film 40 in the fourth embodiment is formed to inhibit theblistering or delaminating of the interlayer insulating film 8 when SiOFis mainly used as described above. However, the present invention is notlimited thereto, but other insulating films may be used as theinterlayer insulating film 8. In this case also, a semiconductor devicehaving a good fuse blow property can be obtained by doing as the fourthembodiment.

Since other parts are the same as those described in the thirdembodiment, the description thereof will be omitted.

Fifth Embodiment

FIG. 14 is a schematic sectional view for illustrating a semiconductordevice 500 in the fifth embodiment of the present invention. FIG. 15 isa schematic diagram showing the cross section of the semiconductordevice 500 in FIG. 14 in the A-A′ direction.

As FIGS. 13 and 14 show, the semiconductor device 500 in the fifthembodiment resembles the semiconductor device 400 described in thefourth embodiment. Similar to the semiconductor device 400, thesemiconductor device 500 also includes an Si substrate 2, an interlayerinsulating film 4, Cu wirings 6, an interlayer insulating film 8, andvia holes 10 filled with tungsten. Also in the fuse portion 510, a fusewiring 12 is formed, and in the bonding pad portion 520, a bonding pad14 is formed. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the fourth embodiment.

Also in the semiconductor device 500, as the semiconductor device 400, asilicon oxide film 50 is formed on the wiring layer whereon the fusewiring 12 is formed. In the semiconductor device 500, however, thesilicon oxide film 50 is not a thin film with a uniform thickness, butincludes a ridged portion 52 formed in the vicinity of the fuse wiring12, and a flat portion 54 on the interlayer insulating film 8. A siliconnitride film 56 is also formed on the silicon oxide film 50. The siliconnitride film 56 is also not a thin film with a uniform thickness, butincludes a ridged portion 58 formed in the vicinity of the fuse wiring12, and a flat portion 60 on the interlayer insulating film 8 as in thesemiconductor device 400.

The silicon oxide film 50 and the silicon nitride film 56 has an openingto expose a part of the surface of the bonding pad 14.

The method for manufacturing the semiconductor device 500 resembles tothe method for manufacturing the semiconductor device 400 described inthe fourth embodiment.

Specifically, steps S102 to S116 are first performed to form the fusewiring 12 in the fuse portion 510, and the bonding pad 14 in the bondingpad portion 520.

Next, as in the fourth embodiment, a silicon oxide film 50 is formed(Step S118). Here, the silicon oxide film 50 is formed using an HDP-CVDmethod. Thereby, the silicon oxide film 50 becomes a thin film includinga ridged portion 52 and a flat portion 54. Here, the formation of thesilicon oxide film 50 is stopped in the stage wherein the silicon oxidefilm 50 is thinner than the thickness d_(f) of the fuse wiring 12. Thethickest portion of the silicon oxide film 50 is still thinner than thethickness d_(f) of the fuse wiring 12.

Next, in the same manner as described for the fourth embodiment, asilicon nitride film 56 is formed on the silicon oxide film 50 using anHDP-CVD method. The thickness of the silicon nitride film 56 is also notuniform, and the ridged portion 58 of the silicon nitride film 56 isformed on the location overlapping the ridged portion 52 of the siliconoxide film 50, and the flat portion 60 of the silicon nitride film 56 isformed. Thereafter, an opening is formed on the bonding pad 14.

Thus, the semiconductor device 500 is manufactured.

Since other parts are the same as in the fourth embodiment, thedescription thereof will be omitted.

According to the fifth embodiment, as described above, the silicon oxidefilm 50 is formed using an HDP-CVD method, and the silicon nitride film56 is formed on the silicon oxide film 50 using an HDP-CVD method.Therefore, the total thickness of the insulating films on the fusewiring 12 can further be thinned compared with the case wherein thesilicon oxide film 50 is formed using a P-CVD method. Therefore, in thesemiconductor device 500, the fuse wiring 12 can be blown more surely.

In the fifth embodiment, the case wherein both the silicon oxide film 50and the silicon nitride film 56 having ridged portions 52, 58, and flatportions 54, 60 are formed using an HDP-CVD method. However, the presentinvention is not limited thereto, but films having the same shapes asthe silicon oxide film 50 and the silicon nitride film 56 may be formedusing other methods.

Since other parts are same as in the forth embodiment, the descriptionthereof will be omitted.

Sixth Embodiment

FIG. 16 is a schematic sectional view for illustrating a semiconductordevice 600 in the sixth embodiment of the present invention. FIG. 17 isa schematic diagram showing the cross section of the semiconductordevice 600 in FIG. 16 in the A-A′ direction.

As FIGS. 15 and 16 show, the semiconductor device 600 in the sixthembodiment resembles the semiconductor device 400 described in thefourth embodiment. Similar to the semiconductor device 400, thesemiconductor device 600 also includes an Si substrate 2, an interlayerinsulating film 4, Cu wirings 6, an interlayer insulating film 8, andvia holes 10 filled with tungsten. Also in the fuse portion 610, a fusewiring 12 is formed, and in the bonding pad portion 620, a bonding pad14 is formed. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the fourth embodiment.

Also in the semiconductor device 600, as the semiconductor device 400, asilicon oxide film 62 is formed on the wiring layer whereon the fusewiring 12 is formed along the step of the fuse wiring 12. In thesemiconductor device 600, however, unlike the semiconductor device 400,a silicon oxide film 64 is further formed on the silicon oxide film 62.The silicon oxide film 64 is not a film with a uniform thickness, butincludes ridged portions 66 formed on the fuse wiring 12, and a flatportion 68 formed between the ridged portions 66. The silicon oxidefilms 62 and 64 have an opening on the bonding pad 14.

The method for manufacturing the semiconductor device 600 resembles tothe method for manufacturing the semiconductor device 400 described inthe fourth embodiment. First, by performing steps S102 to S116, the fusewiring 12 is formed in the fuse portion 610, and a bonding pad 14 isformed in the bonding pad portion 620.

Next, as in the fourth embodiment, a silicon oxide film 62 is formedusing a P-CVD method. Here, the film formation is completed at the stagewherein the thickness of the silicon oxide film 62 is thinner than thethickness d_(f) of the fuse wiring 12.

Next, a silicon oxide film 64 is further formed on the silicon oxidefilm 62 using an HDP-CVD method. When the HDP-CVD method is used, sincethe film is formed simultaneously with etching in the portion having astep, ridged portions 66 and flat portions 68 are formed in the siliconoxide film 64. Thereafter, an opening is formed in the silicon oxidefilms 62 and 64 to expose a portion of the surface of the bonding pad14.

Thereby, the semiconductor device 600 is formed.

According to the sixth embodiment, as described above, the silicon oxidefilm 62 is a thin film with a uniform thickness formed using a P-CVDmethod, and the silicon oxide film 64 is formed on the silicon oxidefilm 62 using an HDP-CVD method. For example, when a silicon oxide filmis formed directly on the interlayer insulating film 8 with a step suchas the fuse wiring 12 as in the second embodiment, the shoulder on thestep, such as the fuse, may be exposed. However, according to the sixthembodiment, a silicon oxide film 62 with a uniform thickness is firstformed along the interlayer insulating film 8 and the overlying fusewiring 12. Therefore, the exposure of the shoulder portion of the fusewiring 12 is prevented, and a semiconductor device having good fuse-blowcharacteristics can be obtained.

In the sixth embodiment, as in the second embodiment, the silicon oxidefilm 64 has ridged portions 66 and flat portions 68. Thereby, asufficient thickness is secured in the silicon oxide films 62 and 64 tocover the sides of the fuse wiring 12, and the total thickness of thesilicon oxide films 62 and 64 can be thinned. Therefore, fuse blow canbe securely performed, and damage to adjacent fuses can be prevented.

Also in the sixth embodiment, as in the second embodiment, the fusewiring 12 is an Al wiring formed on the uppermost layer of the wiringlayers, and the fuse wiring 12 is buried in the oxide film 62.Therefore, the fuse wiring 12 can be blown easily while minimizing theoccurrence of blow residues. In the sixth embodiment, since theformation of a structure wherein an insulating film is sandwichedbetween Al wirings can be avoided, the size of the entire semiconductordevice 600 can be reduced, and the throughput can be improved, whileminimizing the occurrence of cracks during wire bonding.

In the semiconductor device 600, only silicon oxide films 62 and 64 areformed, and no silicon nitride film is formed. However, the presentinvention is not limited thereto, but a silicon nitride film may beformed on the uppermost layer as a passivation film as in the secondembodiment. Thereby, the infiltration of moisture into the chip can besecurely prevented, and furthermore, the reliability of thesemiconductor device 600 can be secured.

Since other parts are same as in the forth embodiment, the descriptionthereof will be omitted.

Seventh Embodiment

FIG. 18 is a schematic sectional view for illustrating a semiconductordevice 700 in the seventh embodiment of the present invention. FIG. 19is a schematic diagram showing the cross section of the semiconductordevice 700 in FIG. 18 in the A-A′ direction.

As FIGS. 17 and 18 show, the semiconductor device 700 in the seventhembodiment resembles the semiconductor device 600 described in the sixthembodiment. Similar to the semiconductor device 600, the semiconductordevice 700 also includes an Si substrate 2, an interlayer insulatingfilm 4, Cu wirings 6, an interlayer insulating film 8, and via holes 10filled with tungsten. Also in the fuse portion 710, a fuse wiring 12 isformed, and in the bonding pad portion 720, a bonding pad 14 is formed.The fuse wiring 12 and the bonding pad 14 have the same thickness d_(f)as in the fourth embodiment.

In the semiconductor device 700, as in the semiconductor device 600, asilicon oxide film 70 and a silicon oxide film 72 are laminated on thewiring layer whereon the fuse wiring 12 is formed. However, unlikesemiconductor device 600, the underlying silicon oxide film 70 is not afilm with a uniform thickness; that is, a film having ridged portions 74and flat portions 76, and the overlying silicon oxide film 72 is a filmwith a uniform thickness. The silicon oxide films 70 and 72 have anopening on the bonding pad 14.

The method for manufacturing the semiconductor device 700 resembles themethod for manufacturing the semiconductor device 600 described in thesixth embodiment.

Specifically, as in the sixth embodiment, by first performing steps S102to S116, the fuse wiring 12 is formed in the fuse portion 710, and abonding pad 14 is formed in the bonding pad portion 720.

Next, as in the sixth embodiment, a silicon oxide film 70 is formed.However, unlike the sixth embodiment, the silicon oxide film 70 havingridged portions 74 and flat portions 76 is formed using an HDP-CVDmethod.

Next, a silicon oxide film 72 is formed on the silicon oxide film 70using a P-CVD method. Here, the silicon oxide film 72 is a film with auniform thickness, and is formed along the ridged portions 74 and theflat portions of the underlying silicon oxide film 70. Thereafter, anopening is formed on the bonding pad 14.

Since other portions are the same as portions in the sixth embodiment,the description thereof will be omitted.

According to the seventh embodiment, as described above, the siliconoxide film 70 is formed using an HDP-CVD method, whereon the siliconoxide film 72 is formed using a P-CVD method. Therefore, even whenetching of the step (shoulder) portion of the fuse wiring 12 proceeds,and the fuse wiring 12 is exposed from the underlying silicon oxide film70 during the formation of the silicon oxide film 70, the silicon oxidefilm 72 is formed thereon, whereby the exposed step portion can becovered. Therefore, since the exposure of the shoulder of the fusewiring 12 can be inhibited, the reliability of the semiconductor devicecan be secured.

In addition, the effects same as the effects described in the sixthembodiment can be obtained in the semiconductor device 700 in theseventh embodiment.

In the semiconductor device 700, silicon nitride film may be formed onthe uppermost layer as a passivation film in order to prevent theinfiltration of moisture into the chip.

Since other parts are same as in the sixth embodiment, the descriptionthereof will be omitted.

Eighth Embodiment

FIG. 20 is a schematic sectional view for illustrating a semiconductordevice 800 in the eighth embodiment of the present invention. FIG. 21 isa schematic diagram showing the cross-section of the semiconductordevice 800 in FIG. 20 in the A-A′ direction.

As FIGS. 19 and 20 show, the semiconductor device 800 resembles thesemiconductor device 200. Similar to the semiconductor device 200, thesemiconductor device 800 also includes an Si substrate 2, an interlayerinsulating film 4, Cu wirings 6, an interlayer insulating film 8, andvia holes 10 filled with tungsten. Also in the fuse portion 810, a fusewiring 12 is formed, and in the bonding pad portion 820, a bonding pad14 is formed. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the first embodiment. As in the second embodiment,a silicon oxide film 20 having a ridged portion 22 and a flat portion24, and a silicon nitride film 26 on the silicon oxide film 20 areformed on the wiring layer whereon the fuse wiring 12 and the bondingpad 14 are formed.

However, the fuse wiring 12 and the bonding pad 14 of the silicon oxidefilm 800 are the laminated structure of TiN/AlCu/TaN in this order fromthe top. Specifically, a TaN film 80 is formed on the surface of theinterlayer insulating film 8, an AlCu film 82 is formed thereon, and aTiN film 84 is formed on the AlCu film 82.

FIG. 22 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 800 in the eighth embodiment of the presentinvention. The method for manufacturing the semiconductor deviceaccording to the eighth embodiment of the present invention will bedescribed below referring to FIGS. 19 to 21.

The method for manufacturing the semiconductor device 800 resembles themethod for manufacturing the semiconductor device 200. As in thesemiconductor device 200, an interlayer insulating film 8 is formed byperforming steps S102 to S114.

Next, a wiring layer for forming the fuse wiring 12 and the bonding pad14 is formed. Specifically, a TaN film 80 is formed (Step S802), an AlCufilm 82 is formed thereon (Step S804), and a TiN film 84 is formed onthe AlCu film 82 (Step S806).

Next, as in the second embodiment, the wiring layer is etched to formthe fuse wiring 12 and the bonding pad 14 (Step S116). Thereafter, asilicon oxide film 20 is formed using an HDP-CVD method, and a siliconnitride film 26 is formed using a P-CVD method. Then, openings areformed (Steps S122, S124), thereby, the semiconductor device 800 isformed.

In the eighth embodiment, as described above, the fuse wiring 12 and thebonding pad 14 have a laminated structure of TiN/AlCu/TaN. Although alaminated structure of TiN/AlCu/TiN/Ti has generally been used otherthan the structure of the Al wiring alone, there has been a problem thatblow residues occur easily when the wiring of this structure is blown asa fuse. This is considered because the melting point of TiN is 2,932° C.and the melting point of Ti is 1,683° C., and two kinds of metals havingdifferent melting points are laminated under the Al wiring. Therefore,the semiconductor device 800, one metal, that is the TiN film 84 alone,is used as the underlying layer of the AlCu film 82. Also, TaN absorbsmore laser beams than TiN. Therefore, according to the eighthembodiment, the semiconductor device 800 having good fuse-blowcharacteristics can be obtained.

Although the case wherein a fuse wiring 12 having a TiN/AlCu/TaNlaminated structure is used is described in the eighth embodiment, thepresent invention is not limited thereto, but other metals may also belaminated.

For example, as a favorable laminated structure of the fuse wiring,TiN/AlCu/TaN/Ta can be considered. The melting point of Ta is 2,996° C.,and the melting point of TaN is 3,088° C. Therefore, even if two kindsof metals are disposed underneath the AlCu film, the blowcharacteristics are not affected because the melting points of the bothmaterials are relatively close to each other. In the eighth embodiment,via holes 10 filled with tungsten connect Cu wirings 6 to the fusewiring 12. However, when such a structure is not used, but the fusewiring 12 is directly connected to Cu wirings 6, due to insufficientcontact to the Cu wirings 6, voids may occur in the boundary causing thedefect of the semiconductor device. However, Ta adheres to Cu betterthan TaN, the use of the TaN/Ta laminated film can improve adhesion withthe Cu wirings 6, and can further improve the reliability of thesemiconductor device.

The examples of other structures as the fuse wiring 12 includeTiN/AlCu/TiN/TaN, or TiN/AlCu/TiN/TaN/Ta. The melting point of TiN is2,932° C., the melting point of TaN is 3,088° C., and the melting pointof Ta is 2,996° C. Therefore, since the melting points of the threematerials are relatively close to each other, the deterioration of blowcharacteristics can be inhibited. Also when the AlCu film directlycontacts the TaN film wherein Ta is insufficiently nitrided, thereaction between Ta and Al may form AlTa to raise the resistance of viaholes. However, according to this structure, direct contact of the AlCufilm with the TaN film can be prevented. Therefore, a semiconductordevice with more stable via resistance can be obtained.

As the other favorable laminated structures for the fuse wiring 12,TiN/AlCu/TiN/Ti/TaN/Ta can be considered. When a TaN/Ta film is formed,exposed to the atmosphere, and a TiN film is formed, the surface of theTaN film may become TaON, and the via resistance may elevate. However,according to this structure, a Ti film is formed on a TaN film, and thena TiN film is formed. Thereby the oxide layer is reduced, and theelevation of via resistance can be inhibited. Therefore, when the fusewiring 12 of this structure is used, a semiconductor device having morestable via resistance can be obtained.

Since other effects are the same as effects described in the secondembodiment, the description thereof will be omitted.

In the eighth embodiment, the case wherein the silicon oxide film 20 andthe silicon nitride film 26 as described in the second embodiment isformed on the fuse wiring 12 of a laminated structure is described.However, in the present invention, the insulating film formed on thefuse wiring 12 is not limited thereto, but for example the insulatingfilms as described in the first to seventh embodiments may also beformed.

Since other parts are same as in the second embodiment, the descriptionthereof will be omitted.

Ninth Embodiment

FIG. 23 is a schematic sectional view for illustrating a semiconductordevice 900 in the ninth embodiment of the present invention. FIG. 24 isa schematic diagram showing the cross-section of the semiconductordevice 900 in FIG. 23 in the A-A′ direction.

As FIGS. 22 and 23 show, the semiconductor device 900 resembles thesemiconductor device 200. Similar to the semiconductor device 200, thesemiconductor device 900 also includes an Si substrate 2, an interlayerinsulating film 4, Cu wirings 6, an interlayer insulating film 8, andvia holes 10 filled with tungsten. Also in the fuse portion 910, a fusewiring 12 is formed, and in the bonding pad portion 920, a bonding pad14 is formed. The fuse wiring 12 and the bonding pad 14 have the samethickness d_(f) as in the first embodiment.

In the semiconductor device 900, however, the interlayer insulating film8 is the laminate of a silicon nitride film 90 and a silicon oxide film92. Via holes 10 are formed so as to pass through the silicon nitridefilm 90 and the silicon oxide film 92, and extend to the wiring layer 6.Here, the silicon nitride film 90 is formed so as to have a thickness of100 nm or more to secure the function as a passivation film.

On the wiring layer whereon a bonding pad 14 and a fuse wiring 12 isformed a silicon oxide film 94. Similar to the silicon oxide film 20 inthe semiconductor device 200, the silicon oxide film 94 has ridgedportions 96 and flat portions 98, and has an opening on the portionwhereon the bonding pad 14 is formed. Also in the semiconductor device900, a silicon nitride film 90 is formed as the interlayer insulatingfilm 8, and since the silicon nitride film 90 acts as a passivationfilm, no silicon nitride film is formed on the silicon oxide film 94.

FIG. 25 is a flow diagram for illustrating the method for manufacturingthe semiconductor device 900 in the ninth embodiment of the presentinvention.

The method for manufacturing the semiconductor device 900 in the ninthembodiment of the present invention will be described below referring toFIGS. 22 to 24.

In the same manner as described in the second embodiment, an interlayerinsulating film 4 is formed on a Si substrate 2, and a Cu wiring 6 isformed (Steps S102 to S104).

Thereafter, a silicon nitride film 90 is formed on the Cu wiring 6 andthe interlayer insulating film 4 (Step S902) using a P-CVD method. Thesilicon nitride film 90 is formed so as to have a thickness of 100 nm ormore. Next, a silicon oxide film 92 is formed on the silicon nitridefilm 90 using a P-CVD method (Step S904). Thereby, the silicon nitridefilm 90 and the silicon oxide film 92 are laminated to form theinterlayer insulating film 8.

Next, via holes 10 passing through the silicon nitride film 90 and thesilicon oxide film 92 are formed by etching (Step S108), and as in thesecond embodiment, steps S110 to S116 are performed to form the fusewiring 12 and the bonding pad 14.

Thereafter, as in the second embodiment, a silicon oxide film 94 isformed on the wiring layer whereon the fuse wiring 12 is formed using anHDP-CVD method (Step S906). Here, the formed silicon oxide film 94 hasflat portions 98 and ridged portions 96. Thereafter, an opening isformed in the silicon oxide film 94 so as to expose a part of thebonding pad 14 (Steps S122, S124).

As described above, the semiconductor device 900 is manufactured.

Here, since the silicon nitride film 90 is formed as the interlayerinsulating film 8, no silicon nitride film acting as a passivation filmis required to form on the silicon oxide film 94.

Since other parts are same as in the second embodiment, the descriptionthereof will be omitted.

According to the ninth embodiment, the interlayer insulating film 8between the Cu wiring 6 and the Al wiring such as the fuse wiring 12 hasa laminated structure consisting of the silicon nitride film 90 and thesilicon oxide film 92. Thereby, even if no silicon nitride film actingas a passivation film is formed on the uppermost layer, sufficientpassivation characteristics, such as the prevention of the infiltrationof moisture into the chip can be secured. It is considered that when asilicon nitride film is formed using a P-CVD method on a silicon oxidefilm formed on an Al wiring, the thickness of the silicon nitride filmis reduced on the sides of the Al wiring leading to the lowering ofpassivation characteristics. In particular, since the distance betweenAl wirings is reduced when the pattern is miniaturized, the coverage ofthe silicon nitride film to the Al wiring leading may decline, andproblems may arise. However, as described in the ninth embodiment, whena part of the interlayer insulating film 8 between the Cu wiring and theAl wiring is formed of the silicon nitride film 90, the semiconductordevice 900 having sufficient passivation characteristics can beobtained.

Since other effects are same as the effects described in the secondembodiment, the description thereof will be omitted.

In the ninth embodiment, a part of the interlayer insulating film 8 isformed of the silicon nitride film 90, the present invention is notlimited thereto, but the entire interlayer insulating film 8 may havethe structure formed of a silicon nitride film. Also, the presentinvention is not limited to the silicon nitride film, but other filmsmay be used as long as passivation characteristics can be secured.

Also in the ninth embodiment, the case wherein a part of the interlayerinsulating film 8 in the semiconductor device 200 described in thesecond embodiment is formed of a silicon nitride film is described.However, the present invention is not limited thereto, but can also beapplied to other structures, for example, structures, as semiconductordevice 100, 600, 700, wherein a silicon oxide film is formed on an Alwiring, or a part of an interlayer insulating film 8 is substituted by asilicon nitride film.

In the present invention, the lower-layer substrates include insulatingfilms and metal wiring layers below the layer whereon a fuse wiring isformed, as well as an Si substrate, and for example, the Si substrate,the interlayer insulating film 4, the Cu wiring 6, and the interlayerinsulating film 8 in first to ninth embodiments fall under thiscategory. Also in the present invention, for example, silicon oxidefilms 40, 50, 62, and 70 in fourth, fifth, sixth, and seventhembodiments fall under the first insulating film; and for example,silicon nitride films 42 and 56, or silicon oxide films 64 and 72 infourth, fifth, sixth, and seventh embodiments fall under the secondinsulating film.

The fuse forming process of the present invention is implemented byperforming steps S114 and S116 in first to seventh and ninthembodiments, or steps S802, S804 and S116 in the eighth embodiment.Also, the silicon oxide film forming process is implemented byperforming, for example, step S118 in the first embodiment; the siliconnitride film forming process is implemented by performing, for example,step S120; and the opening forming process is implemented by performing,for example, step S124.

The features and the advantages of the present invention as describedabove may be summarized as follows.

According to one aspect of the present invention, the insulating filmson the surface of the lower-layer substrate and the fuse are formed sothat the thickness of the insulating film on the lower-layer substrateis thicker than the fuse. Thereby, when the fuse is blown, damage toadjacent fuses can be inhibited, and fuse blow can be properlyperformed.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay by practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No. 2003-101762,filed on Apr. 4, 2003 including specification, claims, drawings andsummary, on which the Convention priority of the present application isbased, are incorporated herein by reference in its entirety.

1-12. (canceled)
 13. A semiconductor device including fuse elementselectrically opened by irradiation with laser light that melts andthereby cuts the fuse elements, the semiconductor device comprising: asemiconductor substrate; a first insulating film supported by saidsemiconductor substrate and including a pair of via holes; fuse elementscomprising respective portions of an aluminum layer disposed on saidfirst insulating film, one of said fuse elements electrically connectingtogether metals filling said pair of via holes in said first insulatingfilm, said pair of metals electrically connecting together a respectivepair of metal wirings; a bonding pad comprising a portion of saidaluminum layer disposed on said first insulating film; a secondinsulating film covering said fuse elements, said first insulating filmbetween said fuse elements, and part of said bonding pad, said secondinsulating film having a first hole through which at least part of saidbonding pad is exposed; and a third insulating film covering said secondinsulating film and having a second hole through which at least part ofsaid bonding pad is exposed, wherein said third insulating film hasplanar portions between said fuse elements and ridged portions oppositesaid fuse elements, and each of said fuse elements is thinner than thetotal thickness of said planar portions of said third insulating filmand said second insulating film at locations between said fuse elements.14. The semiconductor device according to claim 13, wherein said secondinsulating film is a silicon oxide film.
 15. The semiconductor deviceaccording to claim 14, wherein said third insulating film is a siliconoxide film.